115 lines
1.8 KiB
Verilog
115 lines
1.8 KiB
Verilog
module key_matcher(
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input wire clk,
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input wire rst,
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input wire [7:0] scan_code,
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input wire sc_valid,
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output reg [6:0] key_states
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);
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// ---------------
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localparam SC_A = 8'h1C;
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localparam SC_D = 8'h23;
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localparam SC_N4 = 8'h6B;
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localparam SC_N6 = 8'h74;
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localparam SC_N = 8'h31;
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localparam SC_M = 8'h3A;
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localparam SC_ESC = 8'h76;
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localparam SC_REL = 8'hF0;
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// -------------
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reg [15:0] shr;
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always @(posedge clk)
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begin
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if (rst)
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begin
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shr <= 16'b0;
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end
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else if (sc_valid)
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begin
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shr <= { shr[7:0], scan_code };
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end
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end
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wire [7:0] b0 = shr[7:0];
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wire [7:0] b1 = shr[15:8];
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always @(posedge clk)
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begin
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if (rst)
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begin
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key_states <= 6'b0;
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end
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else
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begin
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if ((b0 == SC_A) && (b1 != SC_REL))
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begin
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key_states[0] <= 1'b1;
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end
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else if ((b0 == SC_A) && (b1 == SC_REL))
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begin
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key_states[0] <= 1'b0;
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end
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else if ((b0 == SC_D) && (b1 != SC_REL))
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begin
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key_states[1] <= 1'b1;
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end
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else if ((b0 == SC_D) && (b1 == SC_REL))
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begin
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key_states[1] <= 1'b0;
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end
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else if ((b0 == SC_N4) && (b1 != SC_REL))
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begin
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key_states[2] <= 1'b1;
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end
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else if ((b0 == SC_N4) && (b1 == SC_REL))
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begin
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key_states[2] <= 1'b0;
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end
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else if ((b0 == SC_N6) && (b1 != SC_REL))
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begin
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key_states[3] <= 1'b1;
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end
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else if ((b0 == SC_N6) && (b1 == SC_REL))
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begin
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key_states[3] <= 1'b0;
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end
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else if ((b0 == SC_N) && (b1 != SC_REL))
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begin
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key_states[4] <= 1'b1;
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end
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else if ((b0 == SC_N) && (b1 == SC_REL))
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begin
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key_states[4] <= 1'b0;
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end
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else if ((b0 == SC_M) && (b1 != SC_REL))
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begin
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key_states[5] <= 1'b1;
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end
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else if ((b0 == SC_M) && (b1 == SC_REL))
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begin
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key_states[5] <= 1'b0;
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end
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else if ((b0 == SC_ESC) && (b1 != SC_REL))
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begin
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key_states[6] <= 1'b1;
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end
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else if ((b0 == SC_ESC) && (b1 == SC_REL))
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begin
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key_states[6] <= 1'b0;
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end
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end
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end
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endmodule
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