99 lines
1.5 KiB
Verilog
99 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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`include "src/eth/eth_mac.v"
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module eth_mac_test;
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// Inputs
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reg clk;
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reg rst;
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reg clear;
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wire [7:0] mem_data;
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reg [31:0] ctrl_word;
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// Outputs
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wire [11:0] mem_addr;
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wire TXEN;
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wire [1:0] TXD;
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// Instantiate the Unit Under Test (UUT)
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eth_mac uut (
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.clk(clk),
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.rst(rst),
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.clear(clear),
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.mem_data(mem_data),
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.mem_addr(mem_addr),
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.ctrl_word(ctrl_word),
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.TXEN(TXEN),
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.TXD(TXD)
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);
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always #10 clk <= ~clk;
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reg run;
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// memory
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localparam MEM_SIZE = 445;
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reg [7:0] mem [0:MEM_SIZE-1];
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assign mem_data = mem[mem_addr];
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// frame data
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localparam FRAME_ADDR = 0;
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localparam FRAME_LENGTH = 100;
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localparam START = (1 << 31);
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// RMII deserializer
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integer wrt_cntr;
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reg [7:0] deser;
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always @(posedge clk)
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begin
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if (TXEN && run)
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begin
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deser = {TXD, deser[7:2]}; // right shift
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wrt_cntr = wrt_cntr + 1;
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if ((wrt_cntr & 32'b11) == 0)
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begin
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//$fwrite(ofile, "%c", deser);
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$display("%c", deser);
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end
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end
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end
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initial begin
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// Initialize Inputs
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clk <= 0;
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rst <= 1;
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clear <= 0;
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ctrl_word <= 0;
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deser = 0;
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wrt_cntr = 0;
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run <= 0;
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// populate memory
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$readmemh("src/sim/eth_large_frame_mem.mem", mem);
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// Wait 20 ns for global reset to finish
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#20;
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rst <= 0;
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// Add stimulus here
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#20;
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@(posedge clk);
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ctrl_word <= START | (FRAME_LENGTH << 12) | (FRAME_ADDR);
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run <= 1;
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@(TXEN == 1);
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ctrl_word <= 0;
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@(TXEN == 0);
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#20;
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$finish;
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end
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endmodule
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