epagris/JitMeas-verilog
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Epagris 895d5fc0de operational
2024-12-05 09:57:10 +01:00
.vscode
initial
2024-11-28 17:12:50 +01:00
sims
initial
2024-11-28 17:12:50 +01:00
src
operational
2024-12-05 09:57:10 +01:00
wcfg
operational
2024-12-05 09:57:10 +01:00
.gitignore
operational
2024-12-05 09:57:10 +01:00
Description
High-resolution jitter measurement system for the Xilinx Spartan-6 FPGA.
5.7 MiB
Languages
Verilog 95.8%
Shell 4.2%