JitMeas-verilog/src/stream_mem_init.cgf
2024-11-29 23:57:14 +01:00

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#version3.0
#memory_block_name=stream_init
#block_depth=4096
#data_width=8
#default_word=0
#default_pad_bit_value=0
#pad_direction=left
#data_radix=16
#address_radix=10
#coe_radix=MEMORY_INITIALIZATION_RADIX
#coe_data=MEMORY_INITIALIZATION_VECTOR
#data=
#end