238 lines
3.0 KiB
Verilog
238 lines
3.0 KiB
Verilog
module pp_top(
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input wire clk,
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input wire rst_n,
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output wire [4:0] vga_sigs,
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output wire [3:0] leds_n,
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input wire [3:0] btns_n,
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output wire [7:0] segs_n,
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output wire [3:0] digs_n,
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input wire ps2_ck,
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input wire ps2_dat,
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output wire beep_n
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);
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// bemenetek-kimenetek ponált-negált átalakítása
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wire rst = ~rst_n;
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wire [3:0] btns = ~btns_n;
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assign leds_n = ~leds;
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// 65MHz és 1MHz órajelgenerátor
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wire clk65M;
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wire clk1M;
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wire locked;
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reg srst;
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clk_gen main_clk_gen(
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.areset(rst),
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.inclk0(clk),
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.c0(clk65M),
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.c1(clk1M),
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.locked(locked)
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);
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// -----------
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wire [7:0] data;
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wire valid;
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ps2_host ps2(
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.clk(clk1M),
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.rst(srst),
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.ps2_ck(ps2_ck),
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.ps2_dat(ps2_dat),
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.data(data),
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.valid(valid),
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.ack(1'b1)
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);
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//always @(posedge clk1M)
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//begin
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// if (rst)
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// begin
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// d <= 16'b0;
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// end
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// else if (valid)
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// begin
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// d <= { d[7:0], data };
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// end
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//end
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// -----------
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wire [6:0] ks;
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key_matcher km(
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.clk(clk1M),
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.rst(rst),
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.scan_code(data),
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.sc_valid(valid),
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.key_states(ks)
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);
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// -----------
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// Játéklogika
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wire [9:0] ballx;
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wire [9:0] bally;
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wire [9:0] pod1x;
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wire [9:0] pod2x;
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wire [7:0] score1;
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wire [7:0] score2;
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wire hit;
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wire miss;
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game_controller game (
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.clk(clk1M),
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.rst(srst),
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.start(ks[4]),
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.acknowledge(ks[5]),
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.pod1x(pod1x),
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.pod2x(pod2x),
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.ballx(ballx),
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.bally(bally),
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.move_pod1_en(ks[0] ^ ks[1]),
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.move_pod1_dir(ks[1]),
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.move_pod2_en(ks[2] ^ ks[3]),
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.move_pod2_dir(ks[3]),
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.score1(score1),
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.score2(score2),
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.clear_score(ks[6]),
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.hit(hit),
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.miss(miss)
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);
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wire beep;
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assign beep_n = ~beep;
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beep beeper(
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.clk(clk1M),
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.rst(srst),
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.hit(hit),
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.miss(miss),
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.beep(beep)
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);
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// VGA renderer
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wire hsync;
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wire vsync;
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wire [2:0] rgb;
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vga /* #(
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.COLS(800),
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.ROWS(600),
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.H_FRONT_PORCH(40),
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.H_SYNC_PULSE(128),
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.H_BACK_PORCH(88),
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.V_FRONT_PORCH(1),
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.V_SYNC_PULSE(4),
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.V_BACK_PORCH(23),
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.H_SYNC_NEG(0),
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.V_SYNC_NEG(0)
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) */ vga (
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.pclk(clk65M),
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.sclk(clk1M),
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.rst(srst),
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.hsync(hsync),
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.vsync(vsync),
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.rgb(rgb),
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.pod1x(pod1x),
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.pod2x(pod2x),
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.ballx(ballx),
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.bally(bally)
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);
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assign vga_sigs = { hsync, vsync, rgb };
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// -----------
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wire [3:0] d0;
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wire [3:0] d1;
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wire [3:0] d2;
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wire [3:0] d3;
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assign { d3, d2, d1, d0 } = { score1, score2 };
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//reg [15:0] d;
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//assign { d3, d2, d1, d0 } = d;
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sseg_disp disp(
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.clk(clk1M),
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.rst(srst),
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.d0(d0),
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.d1(d1),
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.d2(d2),
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.d3(d3),
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.dps(4'b0100),
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.segs_n(segs_n),
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.digs_n(digs_n)
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);
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// -----------
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reg [19:0] cntr;
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always @(posedge clk1M, posedge rst)
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begin
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if (rst)
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begin
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cntr <= 0;
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end
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else
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begin
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cntr <= cntr + 1;
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end
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end
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wire tc = &cntr;
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reg reset_issued;
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always @(posedge clk1M, posedge rst)
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begin
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if (rst)
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begin
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reset_issued <= 1'b0;
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srst <= 1'b0;
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end
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else if (tc && !reset_issued)
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begin
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srst <= 1'b1;
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reset_issued <= 1'b1;
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end
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else
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begin
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srst <= 1'b0;
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end
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end
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// -----------
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//always @(posedge clk1M)
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//begin
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// if (rst)
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// begin
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// ld0 <= 0;
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// end
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// else if (tc)
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// begin
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// ld0 <= ~ld0;
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// end
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//end
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wire [3:0] leds = ks[3:0];
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endmodule |