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Mono Color

• 8e3cf978c4 Xtensa_ESP32: Change _iram_end to _iram_text_end Sachin Parekh 2020-02-26 19:08:26 +05:30
• e1b98f0b4b This change prevents tickless idle mode potentially sleeping for an extra tick in the corer case that a tick interrupt occurred between the scheduler being suspended and the expected idle time being checked for a second time (within the idle task) - as described by the sequence below. Th change updates eTaskConfirmSleepModeStatus() to specifically check if a tick is pending, and if so, abort entering sleep mode. RichardBarry 2020-02-28 12:40:11 -08:00
• 499e55a03c
  Bring license in sync with FreeRTOS/FreeRTOS. (#20) Yuhui.Zheng 2020-02-27 14:33:46 -08:00
• 078b400aff Updates vCoRoutineSchedule() so it returns without doing anything if if the co-routine internal data structures have not been initialised. The internal data structures are initialised when the first co-routine is created. NOTE: Co-routines are a deprecated feature. This change was made to close off an old ticket as the source control transitions from SourceForge to Github. ribarry 2020-02-22 17:48:22 -08:00
• 326d88f429
  Added CONTRIBUTING (#18) lundinc2 2020-02-25 16:22:57 -08:00
• c246922ea1
  Small typo on L1287 (#14) AniruddhaKanhere 2020-02-19 14:05:48 -08:00
• 88e32327e9
  version bump to v10.3.1 (#16) V10.3.1-kernel-only Yuhui.Zheng 2020-02-18 22:03:54 -08:00
• 87beba4a4a
  Removing License/license.txt and add LICENSE under root. (#12) Yuhui.Zheng 2020-02-17 09:52:58 -08:00
• 08c9c9151a
  Replacing readme.txt with README.md. (#11) Yuhui.Zheng 2020-02-16 13:18:58 -08:00
• 10bbbcf0b9
  Correct the xTimerCreate() documentation which said NULL was returned if the timer period was passed into the function as 0, whereas that is not the case. (#10) Yuhui.Zheng 2020-02-14 12:16:10 -08:00
• 210b1ffcc8 Re-sync with upstream and stripping away none kernel related. V10.3.0-kernel-only Yuhui Zheng 2020-02-10 13:45:57 -08:00
• 1049fc776a V10.3.0 Richard Barry 2020-02-07 21:58:05 +00:00
• 9c0c37ab9b Added back some TCP/IP stack port layer files. Richard Barry 2020-02-07 21:51:48 +00:00
• 7cf721ccf7 Richard Barry 2020-02-07 21:49:55 +00:00
• 589dd9f149 Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate. Yuhui.Zheng 2020-02-07 20:14:50 +00:00
• f988394e0d Fix spelling issues. Yuhui.Zheng 2020-02-07 19:19:47 +00:00
• 28efb5449c Add "is inside interrupt" function to MPU ports. Make clock setup functions weak symbols in ARMv8-M ports. Update Cortex-M33 ports to use an interrupt mask in place of globally disabling interrupts, as per the other Cortex-M ports. Richard Barry 2020-02-07 01:56:25 +00:00
• 8e5addee1e Update TCP to last release versions in preparation for kernel V10.3.0 release. Richard Barry 2020-02-06 22:45:37 +00:00
• 7bea399061 Update libraries and sundry check-ins ready for the V10.3.0 kernel release. Richard Barry 2020-02-06 18:52:35 +00:00
• d319bb0c71 ESP GCC port -- Added LoadStore Exception handlers. Yuhui.Zheng 2020-01-31 19:31:50 +00:00
• 9fdfbf33e9 Sync FreeRTOS-Labs -CLI -TCP -Trace with the version in FreeRTOS-Plus. Yuhui.Zheng 2020-01-31 19:21:15 +00:00
• ec6f3d77c3 Sync FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP with the version in GitHub at (23665258cabe49d5d68ba23968b6845a7c80eb34). Yuhui.Zheng 2020-01-31 00:07:53 +00:00
• 0c1c85a9dd Removing RISC-V port under ThirdParty. Yuhui.Zheng 2020-01-30 22:23:03 +00:00
• 99e796eb01 Removing unnecessary ThirdParty ports -- Wiced_CY and nrf52840-dk. Yuhui.Zheng 2020-01-30 19:45:03 +00:00
• 4d4493e61a Remove the FreeRTOS-IoT-Libraries from FreeRTOS-Plus as it was an old copy with a newer copy in FreeRTOS-Labs. Richard Barry 2020-01-30 00:05:23 +00:00
• 0d54d1c4dc Correct an err in queue.c introduced when previously updating behaviour when queue sets are used in combination with queue overwrites. Richard Barry 2020-01-29 19:52:38 +00:00
• f5b5b2db04 Cleaning up LPC51U68 projects: - user playable settings are all in FreeRTOSConfig.h. - removed reference to IntQueue.h in main_full.c - readme.txt wording. Yuhui.Zheng 2020-01-24 07:53:14 +00:00
• 2415dc26b0 Introduce the portSOFTWARE_BARRIER macro which thus far is only used by the Win32 demo to hold execution up in case a simulated interrupt is executing simultaneously. That should never happen as all threads should execute on the same core, but we have had numerous reports that this and other Win32 port changes we have made fixed these issues - although we have not been able to replicate them ourselves. Richard Barry 2020-01-23 23:49:24 +00:00
• 18f87e8c33 Add MPU demo project for Nulceo-L152RE which is Coretx-M3. Gaurav Aggarwal 2020-01-23 01:56:36 +00:00
• e058a65b16 Updates to CM3_MPU GCC port Gaurav Aggarwal 2020-01-23 01:50:25 +00:00
• 42a0eaafdc Ensure both one-shot and auto-reload are written consistently with a hyphen in comments. Richard Barry 2020-01-16 04:25:29 +00:00
• 9456992c1f Added uxTimerGetReloadMode() API function. Richard Barry 2020-01-16 04:10:18 +00:00
• c472c5b04f Add MPU demo project for LPC54018 board. Gaurav Aggarwal 2020-01-12 12:33:17 +00:00
• 0d95aca202 Introduce a port for T-HEAD CK802. A simple demo for T-HEAD CB2201 is also included. Yuhui.Zheng 2020-01-10 07:53:14 +00:00
• d2914041f8 Update the GCC and IAR SiFive HiFive rev-b demos to use the new configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS constants in place of the deprecated configCLINT_BASE_ADDRESS constant. Update the IAR RISC-V HiFive demo to use the latest IAR Embedded Workbench version. Richard Barry 2020-01-09 02:28:45 +00:00
• 066e2bc7d2 Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the IAR RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old. Richard Barry 2020-01-09 02:23:51 +00:00
• 75b81a1fab Work in progress update of LPC51U68 MCUXpresso project to rearrange the folder structure and names. Richard Barry 2020-01-09 00:19:36 +00:00
• fbb23055cd Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the GCC RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old. Richard Barry 2020-01-07 01:14:36 +00:00
• eaf9318df8 Add Source/portable/ARMClang file that directs users to the GCC port if they which to use the ARMClang compiler. Richard Barry 2020-01-04 00:14:18 +00:00
• 881958514b If tickless idle mode is in use then ensure prvResetNextTaskUnblockTime() is called after a task is unblocked due to a bit being set in an event group. This allows the MCU to re-enter sleep mode at the earliest possible time (rather than waiting until the timeout that would occur had the task not being unblocked be the event group) and matches a similar change made for queues and derivative objects (semaphores, etc.) some time ago. Richard Barry 2020-01-03 22:50:31 +00:00
• 853856e8cc Correct #error text in multiple fat file system files. Richard Barry 2020-01-03 20:53:27 +00:00
• 9e86cb95a7 Add xPortIsInsideInterrupt() to the IAR ARMv7-M ports. Richard Barry 2020-01-03 01:17:29 +00:00
• be3561ed53 Added xTaskAbortDelayFromISR() and ulTaskNotifyValueClear() API functions. Added tests for xTaskAbortDelayFromISR() into Demo/Common/Minimal/AbortDelay.c. Added tests for ulTaskNotifyValueClear() into Demo/Common/Minimal/TaskNotify.c. Richard Barry 2020-01-02 18:55:20 +00:00
• 0a29d350b1 Renamed RISC-V_RV32_SiFive_HiFive1_IAR directory to RISC-V_RV32_SiFive_HiFive1-RevB_IAR as it targets the RevB hardware. Richard Barry 2020-01-01 22:38:23 +00:00
• 62b413627a Minor updates to comment block for xTaskCheckForTimeOut(). Richard Barry 2020-01-01 22:24:44 +00:00
• dfc1bf8ec3 Rename RISC-V_RV32_SiFive_HiFive1-FreedomStudio directory to RISC-V_RV32_SiFive_HiFive1-RevB-FreedomStudio as it targets Rev B of the hardware. Richard Barry 2020-01-01 22:05:35 +00:00
• 4b943b35e0 Update RISCC-V-RV32-SiFive_HiFive1_FreedomStudio project to latest tools and metal library versions. Richard Barry 2020-01-01 22:02:06 +00:00
• cfa83672ef Rename STM32Cube to GCC for STM32L4 Discovery projects as GCC is the compiler used. Gaurav Aggarwal 2020-01-01 00:35:42 +00:00
• 474182ab39 Make vSetupTimerInterrupt weak in the RVDS M4 MPU port to give the application writer a chance to override this function. This gives the application write ability to use a different timer. Gaurav Aggarwal 2020-01-01 00:04:10 +00:00
• 22dd9a55ab Update documentation of xTaskCheckForTimeOut function to reflect the intended use of this API. Gaurav Aggarwal 2019-12-31 20:49:07 +00:00
• 8f0eaf274c - Updates to projects due to demo folder name change. (IAR source file paths and assembler path were fixed. Keil source file paths were fixed.) - Added back power static library for GCC and IAR. (Power management related interface definitions are in drivers/fsl_power.h. power.c is empty due to "implementation is in header file and power library") - Note for GCC link: the command used for linking is arm-none-eabi-gcc -nostdlib -L<additional lib search path> -Xlinker ... -o "CORTEX_M0+_LPC51U68_LPCXpresso.axf" <all *.o> -lpower. Per GCC doc, static library name in file system is libpower.a. Yuhui.Zheng 2019-12-31 08:06:33 +00:00
• 3203c5cc85 Previously the STM32F0518 compiler setting was changed to enable the use of the __weak attribute - however changing the port layer to use #pragma weak in place of __weak means the compiler setting change is not required and removes the risk of introducing incompatibilities - so this check in reverts the compiler settings change. Richard Barry 2019-12-30 22:24:58 +00:00
• cc673eb6a5 Ensure the CORTEX_M0_STM32F0518_IAR demo builds after updates to the Cortex-M0 port layer - required an update to the project settings to allow IAR extensions as the port layer now uses the _weak qualifier. Richard Barry 2019-12-30 22:07:33 +00:00
• 801e63bd10 Ensure the LPC1114 demo still builds after updates to the Cortex-M0 port layer - includes minor update to remove compiler warning that resulted from a newer compiler version. Richard Barry 2019-12-30 22:00:26 +00:00
• 53c98357b0 Ensure the LPC1114 demo still builds after updates to the Cortex-M0 port layer - includes minor update to remove compiler warning that resulted from a newer compiler version. Richard Barry 2019-12-30 21:59:11 +00:00
• 49052a6581 Ensure the XMC1000_IAR_KEIL_GCC projects still build after updates to the Cortex-M0 port layer - minor change to remove warning related to using a newer version of the IAR tools. Richard Barry 2019-12-30 21:44:22 +00:00
• e292c67933 Replace the static prvSetupTimerInterrupt() function in the Cortex-M port layers that still used it (other than MPU ports so far) with a weakly defined function call vPortSetupTimerInterrupt() - which allows application writers to override the function with one that uses a different clock. Richard Barry 2019-12-30 21:16:09 +00:00
• e23d638afd Correct use of xStreamBufferRead() to xStreamBufferReceive() in code comments - no source code changes. Richard Barry 2019-12-30 20:00:49 +00:00
• c72df2f98d Tidy up comments only. Richard Barry 2019-12-27 21:22:07 +00:00
• 7ddea8fc8b Enable the Win32 comprehensive test/demo build and run when configUSE_QUEUE_SETS is set to 0. Richard Barry 2019-12-27 21:02:23 +00:00
• 70dbc12579 Update the LM3Sxxxx_IAR_Keil demo so the IAR project writes to the UART and executes in QEMU. Richard Barry 2019-12-27 20:59:57 +00:00
• cef6548e8b Updates to CM4_MPU RCDS port Gaurav Aggarwal 2019-12-24 22:45:32 +00:00
• 18c3e5e02a Remove local paths from the URL files Gaurav Aggarwal 2019-12-24 19:16:19 +00:00
• 05adf564f6 Add readme into the third party RISC-V port that points to the directories that contains the official ports. Richard Barry 2019-12-24 17:24:23 +00:00
• ce7e8b87d8 Add IAR MPU project for STM32L475 Discovery Kit IoT Node Gaurav Aggarwal 2019-12-21 00:04:04 +00:00
• 96b6746364 Updates to CM4_MPU IAR port Gaurav Aggarwal 2019-12-21 00:02:31 +00:00
• b27fb82bc1 Increase test coverage for queue sets. Rename the CORTEX_M0+_LPC51U68_LPCXpresso demo to CORTEX_M0+_LPC51U68_GCC_IAR_KEIL as it supports all three compilers. Richard Barry 2019-12-20 02:54:30 +00:00
• b55bbe55ac Remove build files accidentally checked in. Remove the CMSIS math library as it is large and not used. Richard Barry 2019-12-20 02:49:15 +00:00
• 47c666bb1e Add MPU projects for STM32L475 Discovery Kit IoT Node Gaurav Aggarwal 2019-12-20 02:07:09 +00:00
• 47d8ac6ac6 Updates to CM4_MPU GCC port Gaurav Aggarwal 2019-12-20 02:05:44 +00:00
• c07f60c383 Adding GCC/Keil/IAR projects for NXP LPC51U68 (CM0+). Yuhui.Zheng 2019-12-18 10:06:30 +00:00
• 9c0e3fe9f1 Cortex M0 GCC/IAR/Keil ports -- tickless support. Yuhui.Zheng 2019-12-18 09:55:08 +00:00
• 3cde02a046 RVDS/Keil weak linkage for vPortSetupTimerInterrupt() -- CM4F, CM3 Yuhui.Zheng 2019-12-18 02:08:06 +00:00
• d58e6a7b09 Use linker script variables for MPU setup for Nuvoton M2351 Keil Project Gaurav Aggarwal 2019-12-17 01:45:53 +00:00
• d449c8979d Use the linker script variables for MPU setup for Keil Simulator Demo Gaurav Aggarwal 2019-12-17 00:14:26 +00:00
• 66ce9f7d72 Move warning suppression for IAR compiler to portmacro.h for v8M ports Gaurav Aggarwal 2019-12-07 01:23:17 +00:00
• 1deeb6dd84 Check socket binding result before doing anything with socket. (This is to address ARG findings.) Breaking the single return rule here, due to precedent violation at line 1039 and 1144. Yuhui.Zheng 2019-12-04 07:52:49 +00:00
• 9491af1fd7 Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to overwrite items in two queues that are part of the same set. Minor queue optimisations. Richard Barry 2019-12-03 01:50:07 +00:00
• e5708b38e9 Add the Labs projects provided in the V10.2.1_191129 zip file. Richard Barry 2019-12-02 23:39:25 +00:00
• 46e5937529 Remove guards against __ARMCC_VERSION version numbers that were previously used to avoid compiler warnings in some GCC ARM Cortex ports. Richard Barry 2019-11-21 22:35:21 +00:00
• d1fb8907ab Add software timer to the Win32 blinky demo. Richard Barry 2019-11-18 17:35:40 +00:00
• 07622ed3ee Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project. Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack. Richard Barry 2019-11-18 17:23:14 +00:00
• 16639d2d63 Update to the latest atomic.h. Improve commenting in RISC-V GCC port. Fix IAR RISC-V port so the first task starts with interrupts enabled. Add references to third party page ref using newlib with FreeRTOS into the tasks.c file in each place newlib is referenced. Move the position of the traceTASK_DELETE() trace macro in case of use with a memory allocator that writes over freed memory even when inside a critical section. Efficiency improvement: Make sure xTaskIncrementTick() does not return pdTRUE when the scheduler is locked. This just prevents an unnecessary yield interrupt (unnecessary as it is ignored) when xYieldPending happens to be pdTRUE. Richard Barry 2019-11-18 16:28:03 +00:00
• 18916d5820 Rename the RISC-V_RV32_SiFive_Hifive1_GCC folder to RISC-V_RV32_SiFive_HiFive1_FreedomStudio as it is built with Freedom Studio. Richard Barry 2019-10-22 22:30:06 +00:00
• 5306ba245d Add nano-specs linker option to HiFive1_GCC demo. Richard Barry 2019-10-22 22:27:55 +00:00
• c0741e36ed Fix spelling mistakes copied and pasted into a couple of RISC-V demo main.c files. Richard Barry 2019-10-22 16:31:57 +00:00
• fccc445865 Change version and license text in RISC-V_RV32_SiFive_HiFive1_GCC FreeRTOSConfig.h file. Richard Barry 2019-10-22 02:17:15 +00:00
• 11c391dfb3 Tidy up main_full.c and change alignment of variable accesses in RegTest.S for the RISC-V_Renode_Emulator_SoftConsole demo. Richard Barry 2019-10-22 02:15:28 +00:00
• 343fbe795f Rework RISC-V QEMU example to use vanilla Eclipse in place of Freedom Studio. NOTE: RISC-V QEMU mtime interrupts are not generated consistently. Richard Barry 2019-10-22 02:03:15 +00:00
• ef31243396 Add some asserts into the common demo tasks to catch scenarios where the tasks are not being used but the part of the demo/test that gets called from the tick hook is called resultant in an access to objects that were not created. Richard Barry 2019-10-21 17:17:34 +00:00
• 61a003088d Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time. Richard Barry 2019-10-21 04:16:32 +00:00
• a83244a37e Add the miv-basic.resc reNode script into the RISC-V_Renode_Emulator_SoftConsole demo as it is no longer shipped with the Microsemi tools. Richard Barry 2019-10-17 20:39:40 +00:00
• c7c60cff15 Rename RISC-V-Qemu-sive_e_Freedom_Studio directory to RISC-V-Qemu-sifive_e-Eclipse-GCC as it is now using Vanilla Eclipse and vanilla GCC in place of Freedom Studio. Richard Barry 2019-10-16 04:31:57 +00:00
• f78ccd077a Recreate the RISC-V-Qemu demo using Vanilla Eclipse in place of Freedom Studio as there is not a new Freedom Studio project that targets the HiFive1 board, and the updated Freedom Studio version didn't work with this project any more anyway. Richard Barry 2019-10-16 04:28:28 +00:00
• d435a7b62d Move the call to traceTASK_DELETE() to before port portPRE_TASK_DELETE_HOOK() as in the Windows port portPRE_TASK_DELETE_HOOK() never returns. Richard Barry 2019-10-15 22:14:40 +00:00
• 4922cff4ce Add IAR demo for the SiFive RISC-V HiFive Rev B board. Richard Barry 2019-10-14 03:20:18 +00:00
• f6edf4adf9 Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code. Richard Barry 2019-10-14 00:16:25 +00:00
• 96e61a10a5 Tidy up the RISC-V_RV32_SiFive_HiFive1_GCC demo ready for its eventual release. Richard Barry 2019-10-14 00:04:53 +00:00
• d4216903d9 Added the "full" demo to the RISC-V_RV32_SiFive_HiFive1_GCC demo - backup check in only as still a work in progress. Richard Barry 2019-10-13 22:53:00 +00:00
• 71d9450836 RIS-V_RV32_SiFive_HiFive1_GCC project now running the blinky demo - still a work in progress. Richard Barry 2019-10-11 02:59:13 +00:00