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This commit is contained in:
Wiesner András 2024-12-05 09:57:10 +01:00
parent fbe6667fe6
commit 895d5fc0de
28 changed files with 2465 additions and 73 deletions
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3
.gitignore vendored Normal file
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@ -0,0 +1,3 @@
*.out
*.vcd
*.sav

27
src/cdc.v Normal file
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@ -0,0 +1,27 @@
`timescale 1ns / 1ps
module cdc (
input tclk, // target domain's clock
input rst,
input sin, // input data from the source domain
output tout // output data to the target domain
);
reg [1:0] pipe;
always @(posedge tclk)
begin
if (rst)
begin
pipe <= 0;
end
else
begin
pipe[0] <= sin;
pipe[1] <= pipe[0];
end
end
assign tout = pipe[1];
endmodule

42
src/clkdiv.v Normal file
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@ -0,0 +1,42 @@
`timescale 1ns / 1ps
module clkdiv #(
parameter DIV = 2,
// AUTOCALCULATED
parameter HALFDIV = DIV / 2,
parameter CNTR_MSB = $clog2(DIV) - 1
)(
input clk, rst, clear, // general signals
output pos, neg, // output strobes corresponding to rising and falling edges
output sclk // output clock
);
wire rstclr = rst || clear;
reg [CNTR_MSB:0] cntr;
always @(posedge clk)
begin
if (rstclr)
begin
cntr <= 0;
end
else
begin
if (cntr == (DIV - 1'b1))
begin
cntr <= 0;
end
else
begin
cntr <= cntr + 1'b1;
end
end
end
assign sclk = cntr < HALFDIV;
assign pos = cntr == 0;
assign neg = cntr == HALFDIV;
endmodule

117
src/del_meas/del_meas.v
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@ -1,47 +1,130 @@
`timescale 1ns / 1ps
module del_meas #(
parameter WIDTH = 10
parameter WIDTH = 10,
// AUTOCALCULATED
parameter DEL_MAX_TICK = (1 << WIDTH) - 1 // maximum delay that can be handled
)(
input wire clk, // clock
input wire rst, // reset
input clk, // clock
input rst, // reset
input clear, // clear
input wire ref, // reference signal
input wire sig, // signal being measured
input ref, // reference signal
input sig, // signal being measured
input wire arm, // arm the next measurement cycle
output wire listening, // indicated that measurement is armed
output reg done, // signals when measurement has concluded
input wire ack, // acknowledge latest measurement, turn off done
input arm, // arm the next measurement cycle
output listening, // indicates that measurement is armed
output done, // signals when measurement has concluded
input ack, // acknowledge latest measurement, turn off done
output reg negative, // indicates if delay is negative
output reg [WIDTH-1:0] delay // delay in ticks
output reg [WIDTH-1:0] delay, // delay in ticks
output [2:0] state_dbg
);
// named states
localparam S_IDLE = 2'b0;
localparam S_LISTEN = 2'b1;
wire rstclr = rst || clear;
// inner state
reg [1:0] state;
// named states
localparam S_IDLE = 3'b001;
localparam S_LISTEN = 3'b010;
localparam S_MEASURE = 3'b100;
// first edge associations
localparam FE_REF = 1'b0;
localparam FE_SIG = 1'b1;
reg [2:0] state; // FSM state
reg arm_prev, ref_prev, sig_prev, ack_prev; // various input values in the previous cycle
wire arm_edge = arm && !arm_prev; // there was a transition on the arm input
wire ref_edge = !ref && ref_prev; // there was a transition in the reference
wire sig_edge = !sig && sig_prev; // there was a transition in the signal
reg first_edge; // stores the signal transitioned first
wire end_meas = (first_edge == FE_REF) ? sig_edge : ref_edge; // end meas pulse
wire ack_pulse = ack && !ack_prev; // ack line has been pulsed
reg acked; // acknowledge in the previous cycle, used for done masking
// main state machine
always@(posedge clk)
begin
if (rst)
if (rstclr)
begin
done <= 0;
negative <= 0;
delay <= 0;
arm_prev <= 0;
ref_prev <= 0;
sig_prev <= 0;
state <= S_IDLE;
first_edge <= FE_REF;
acked <= 1;
ack_prev <= 0;
end
else
begin
// retain specific inputs
arm_prev <= arm;
ref_prev <= ref;
sig_prev <= sig;
ack_prev <= ack;
// save acknowledgement
if (ack_pulse)
begin
acked <= 1;
end
// delay counter with saturation
if ((state == S_MEASURE) && (delay < DEL_MAX_TICK))
begin
delay <= delay + 1'b1;
end
// state machine
case (state)
S_IDLE: if (arm_edge) state <= S_LISTEN;
S_LISTEN:
if (sig_edge || ref_edge)
begin
delay <= 0; // reset the delay
if (sig_edge && ref_edge) // both signals transitioned in the same time slot
begin
negative <= 0;
state <= S_IDLE;
acked <= 0;
end
else // only a single transision was detected
begin
state <= S_MEASURE;
first_edge <= sig_edge ? FE_SIG : FE_REF; // store which signal produced the first edge
negative <= sig_edge; // delay is negative, if signal edge comes first
end
end
S_MEASURE:
if (end_meas)
begin
state <= S_IDLE;
acked <= 0;
end
default:
begin
state <= S_IDLE;
acked <= 0;
end
endcase
end
end
// output logic
assign listening = (state == S_LISTEN);
assign done = (state == S_IDLE) && (!acked);
assign state_dbg = state;
endmodule

65
src/del_meas/del_meas_cdc.v Normal file
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`timescale 1ns / 1ps
`include "src/del_meas/del_meas.v"
module del_meas_cdc #(
parameter WIDTH = 10
)(
input clkMeas, clkIntf, rst, clear,
input ref, sig, arm, ack,
output listening, done, negative, [WIDTH-1:0] delay, [2:0]state_dbg
);
wire arm_M, ack_M, listening_M, done_M;
cdc arm_cdc (
.tclk(clkMeas),
.rst(rst),
.sin(arm),
.tout(arm_M)
);
cdc ack_cdc (
.tclk(clkMeas),
.rst(rst),
.sin(ack),
.tout(ack_M)
);
cdc listening_cdc (
.tclk(clkIntf),
.rst(rst),
.sin(listening_M),
.tout(listening)
);
cdc done_cdc (
.tclk(clkIntf),
.rst(rst),
.sin(done_M),
.tout(done)
);
del_meas #(
.WIDTH(WIDTH)
) del_meas_nocdc (
.clk(clkMeas),
.rst(rst),
.clear(clear),
.ref(ref),
.sig(sig),
.arm(arm_M),
.listening(listening_M),
.done(done_M),
.ack(ack_M),
.negative(negative),
.delay(delay),
.state_dbg(state_dbg)
);
endmodule

1
src/eth/eth_mac.v
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@ -1,7 +1,6 @@
`timescale 1ns / 1ps
`include "src/eth/mac_memory_access_controller.v"
`include "src/rmii/rmii_clock_generator.v"
`include "src/rmii/rmii_transmit_controller.v"
module eth_mac #(

43
src/eth/mac_memory_access_controller.v
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@ -9,7 +9,8 @@ module mac_memory_access_controller #(
// AUTOCALCULATED
parameter DATA_MSB = DATA_WIDTH - 1,
parameter ADDR_MSB = ADDR_WIDTH - 1,
parameter LEN_MSB = 10
parameter LEN_MSB = 10,
parameter MIN_FRAME_SIZE = 6'd60
)(
input clk, rst, clear, // general signals
@ -31,15 +32,25 @@ module mac_memory_access_controller #(
// --------------
wire clear_crc = (state == IDLE);
wire crc_en = (state == FETCH_FRAME) && tx_not_full;
wire crc_en = ((state == FETCH_FRAME) || (state == INSERT_PADDING)) && tx_not_full;
wire [31:0] crc_out;
// override CRC input when zero padding is applied
reg [DATA_WIDTH-1:0] crc_in;
always @(*)
begin
case (state)
INSERT_PADDING: crc_in <= 8'h00;
default: crc_in <= mem_data;
endcase
end
crc32 crc32_engine (
.clk(clk),
.rst(rst),
.clear(clear_crc | clear),
.data_in(mem_data),
.data_in(crc_in),
.crc_en(crc_en),
.crc_out(crc_out)
);
@ -52,8 +63,9 @@ wire rstclr = rst | clear;
localparam IDLE = 0;
localparam INSERT_PREAMBLE = 1;
localparam FETCH_FRAME = 2;
localparam APPEND_CRC = 3;
localparam WAIT_TX_COMPL = 4;
localparam INSERT_PADDING = 3;
localparam APPEND_CRC = 4;
localparam WAIT_TX_COMPL = 5;
// main state machine
reg [2:0] state;
@ -67,6 +79,7 @@ reg [2:0] preamble_idx; // index of the preamble byte being sent
reg [1:0] crc_idx; // index of the CRC bytes
reg [LEN_MSB:0] len_left; // remaining bytes to be transmitted
reg [5:0] pad_left; // padding left
always @(posedge clk)
begin
@ -78,6 +91,7 @@ begin
len_left <= 0;
preamble_idx <= 0;
crc_idx <= 0;
pad_left <= 0;
end
else
begin
@ -88,6 +102,7 @@ begin
len_left <= frame_len - 1'b1;
preamble_idx <= 0;
crc_idx <= 0;
pad_left <= (frame_len < MIN_FRAME_SIZE) ? (MIN_FRAME_SIZE - frame_len - 1'b1) : 0;
end
INSERT_PREAMBLE:
@ -109,6 +124,14 @@ begin
end
end
end
INSERT_PADDING:
begin
if (tx_not_full)
begin
pad_left <= pad_left - 1'b1;
end
end
APPEND_CRC:
begin
@ -125,8 +148,9 @@ begin
// next state logic
case (state)
IDLE: if (start && frame_params_valid) state <= INSERT_PREAMBLE;
INSERT_PREAMBLE: if (preamble_idx == (PREAMBLE_LEN - 1)) state <= FETCH_FRAME;
FETCH_FRAME: if ((len_left == 0) && tx_not_full) state <= APPEND_CRC;
INSERT_PREAMBLE: if ((preamble_idx == (PREAMBLE_LEN - 1)) && tx_not_full) state <= FETCH_FRAME;
FETCH_FRAME: if ((len_left == 0) && tx_not_full) begin if (pad_left != 0) state <= INSERT_PADDING; else state <= APPEND_CRC; end
INSERT_PADDING: if ((pad_left == 0) && tx_not_full) state <= APPEND_CRC;
APPEND_CRC: if ((crc_idx == (3)) && tx_not_full) state <= WAIT_TX_COMPL;
WAIT_TX_COMPL: if (!transmitter_busy) state <= IDLE;
default: state <= IDLE;
@ -137,13 +161,14 @@ end
// combinatorial outputs
assign busy = (state != IDLE);
//assign tx_data_in = mem_data;
assign tx_wrt = (state == FETCH_FRAME) || (state == INSERT_PREAMBLE) || (state == APPEND_CRC);
assign tx_wrt = (state == INSERT_PREAMBLE) || (state == FETCH_FRAME) || (state == INSERT_PADDING) || (state == APPEND_CRC);
// assign data output
always @(*)
begin
case (state)
INSERT_PREAMBLE: tx_data_in <= (preamble_idx == (PREAMBLE_LEN - 1)) ? SOF_PATTERN : PREAMBLE_PATTERN;
INSERT_PREAMBLE: tx_data_in <= (preamble_idx == (PREAMBLE_LEN - 1'b1)) ? SOF_PATTERN : PREAMBLE_PATTERN;
INSERT_PADDING: tx_data_in <= 8'h00;
APPEND_CRC:
case (crc_idx)
2'd3: tx_data_in <= crc_out[31:24];

93
src/io_controller.v Normal file
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@ -0,0 +1,93 @@
`timescale 1ns / 1ps
`include "src/clkdiv.v"
module io_controller #(
parameter CLK_DIV = 100,
parameter FRAME_SIZE = 16,
// AUTOCALCULATED
parameter FRAME_IDX_MSB = $clog2(FRAME_SIZE - 1) - 1
)(
input clk, rst, clear,
input [7:0] leds,
output reg [7:0] sw,
output mosi,
input miso,
output load,
output sclk,
output rstn
);
wire rstclr = rst || clear;
wire strobe;
clkdiv #(
.DIV(CLK_DIV)
) sclk_div (
.clk(clk),
.rst(rst),
.clear(clear),
.sclk(sclk),
.pos(),
.neg(strobe)
);
reg [FRAME_SIZE-1:0] data;
reg [FRAME_IDX_MSB:0] idx;
always @(posedge clk)
begin
if (rstclr)
begin
data <= 0;
sw <= 0;
end
else
begin
if (strobe)
begin
if (idx == (FRAME_SIZE - 1'b1))
begin
sw <= data[7:0];
data <= {miso, 7'b0, leds};
end
else
begin
data <= {miso, data[15:1]};
end
end
end
end
always @(posedge clk)
begin
if (rstclr)
begin
idx <= (FRAME_SIZE - 1'b1);
end
else
begin
if (strobe)
begin
if (idx == (FRAME_SIZE - 1'b1))
begin
idx <= 0;
end
else
begin
idx <= idx + 1'b1;
end
end
end
end
assign rstn = !rstclr;
assign load = idx == (FRAME_SIZE - 1'b1);
assign mosi = data[0];
endmodule

46
src/isync.v Normal file
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@ -0,0 +1,46 @@
`timescale 1ns / 1ps
module isync #(
parameter STAGES = 3,
parameter WIDTH = 1,
// AUTOCALCULATED
parameter GEN_STAGES = STAGES - 1,
parameter GEN_STAGES_MSB = STAGES - 2
)(
input clk, rst,
input [WIDTH-1:0] in,
output [WIDTH-1:0] out
);
(* iob="force" *)
reg [WIDTH-1:0] first;
reg [WIDTH-1:0] stages[GEN_STAGES_MSB:0];
integer i;
always @(posedge clk)
begin
if (rst)
begin
first <= 0;
for (i = 0; i < GEN_STAGES; i = i + 1)
begin
stages[i] <= 0;
end
end
else
begin
first <= in;
stages[0] <= first;
for (i = 1; i < GEN_STAGES; i = i + 1)
begin
stages[i] <= stages[i - 1];
end
end
end
assign out = stages[GEN_STAGES_MSB];
endmodule

209
src/jitmeas_top.v
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@ -1,27 +1,73 @@
`timescale 1ns / 1ps
`include "src/eth/eth_mac.v"
`include "src/del_meas/del_meas_cdc.v"
module jitmeas_top(
input clk50, rst, clear,
input clk50, clk200, rst, clear,
input btn,
input [2:0] btn,
output [7:0] leds,
input [7:0] sw,
output REF_CLK,
//input [1:0] RXD,
//input CRS_DV,
output [1:0] TXD,
output TXEN
output TXEN,
input sig, ref
);
localparam MAIN_CLK_FREQ = 150; // Main Clock Frequency in MHz
/* configuration */
localparam MEM_DATA_WIDTH = 8; // Memory word size
localparam MEM_ADDR_WIDTH = 12; // Memory address size
localparam DM_WIDTH = 7; // Width of the delay measurement counter
localparam FRAME_LENGTH = 2; // Frame payload size
/* LEDs and switches */
assign leds = {sig_synced, ref_synced, pckt_full, pckt_empty, dm_state, dm_enable};
/* SIG and REF signals synchronized to the default domain */
wire sig_synced, ref_synced;
cdc sig_jm_cdc (
.tclk(clk50),
.rst(rst),
.sin(sig),
.tout(sig_synced)
);
cdc ref_jm_cdc (
.tclk(clk50),
.rst(rst),
.sin(ref),
.tout(ref_synced)
);
/* Data stream memory */
wire [MEM_DATA_WIDTH-1:0] stream_mem_data;
wire [MEM_ADDR_WIDTH-1:0] stream_mem_addr;
wire stream_mem_wea;
wire [MEM_ADDR_WIDTH-1:0] stream_mem_addra;
wire [MEM_DATA_WIDTH-1:0] stream_mem_dina;
wire [31:0] ctrl_word;
StreamMemory stream_mem (
/* PORT A */
.clka(clk50), // input clka
.wea(stream_mem_wea), // input [0 : 0] wea
.addra(stream_mem_addra), // input [10 : 0] addra
.dina(stream_mem_dina), // input [15 : 0] dina
/* PORT B */
.clkb(clk50), // input clkb
.rstb(rst), // input rstb
.addrb(stream_mem_addr), // input [11 : 0] addrb
.doutb(stream_mem_data) // output [7 : 0] doutb
);
/* Ethernet MAC */
wire [31:0] mac_ctrl_word;
eth_mac #(
.MEM_DATA_WIDTH(MEM_DATA_WIDTH),
@ -34,30 +80,55 @@ eth_mac #(
.mem_data(stream_mem_data),
.mem_addr(stream_mem_addr),
.ctrl_word(ctrl_word),
.ctrl_word(mac_ctrl_word),
.TXEN(TXEN),
.TXD(TXD)
);
StreamMemory stream_mem (
/* PORT A */
.clka(clk50), // input clka
.ena(1'b0), // input ena
.wea(1'b0), // input [0 : 0] wea
.addra(12'b0), // input [10 : 0] addra
.dina(8'b0), // input [7 : 0] dina
/* transmission scheduler and packetizer */
reg [MEM_DATA_WIDTH-1:0] pckt_data_in;
wire pckt_wrt;
wire pckt_immtx;
wire pckt_empty;
wire pckt_full;
/* PORT B */
.clkb(clk50), // input clkb
.rstb(rst), // input rstb
.addrb(stream_mem_addr), // input [10 : 0] addrb
.doutb(stream_mem_data) // output [7 : 0] doutb
packetizer #(
.MEM_WRITE_WIDTH(MEM_DATA_WIDTH),
.MEM_DEPTH_BYTE(2**MEM_ADDR_WIDTH)
) tx_packetizer (
.clk(clk50),
.rst(rst),
.clear(clear),
.mac_ctrl_word(mac_ctrl_word),
.data_in(pckt_data_in),
.wrt(pckt_wrt),
.mem_wea(stream_mem_wea),
.mem_data(stream_mem_dina),
.mem_addr(stream_mem_addra),
.immtx(pckt_immtx),
.empty(pckt_empty),
.full(pckt_full)
);
clkdiv #(
.DIV(25000000)
) pckt_tx_sched (
.clk(clk50),
.rst(rst),
.clear(clear),
.sclk(),
.pos(pckt_immtx),
.neg()
);
/* button handling */
reg btn_prev;
reg [2:0] btn_prev;
always @(posedge clk50)
begin
if (rst | clear)
@ -70,11 +141,99 @@ begin
end
end
localparam FRAME_LENGTH = 100;
//reg mac_transmit;
//assign mac_ctrl_word[30:0] = 31'b0 | (FRAME_LENGTH << MEM_ADDR_WIDTH) | (0);
//assign mac_ctrl_word[31] = (~btn_prev[0] && btn[0]) | mac_transmit;
/* measurement handling */
wire dm_start = ~btn_prev[1] && btn[1];
wire dm_enable = sw[0];
reg dm_arm;
wire dm_done;
reg dm_ack;
wire [2:0] dm_state;
wire dm_negative;
wire [DM_WIDTH-1:0] dm_delay;
del_meas_cdc #(
.WIDTH(DM_WIDTH)
) del_meas_inst (
.clkMeas(clk200),
.clkIntf(clk50),
.rst(rst),
.clear(clear),
.ref(ref),
.sig(sig),
.arm(dm_arm),
.listening(),
.done(dm_done),
.ack(dm_ack),
.negative(dm_negative),
.delay(dm_delay),
.state_dbg(dm_state)
);
/* measurement data handling */
// convert delay to a signed value
wire [DM_WIDTH:0] signed_delay = dm_negative ? (~({1'b0, dm_delay} + 1'b1)) : {1'b0, dm_delay};
reg dm_done_prev;
assign pckt_wrt = dm_done && !dm_done_prev;
always @(posedge clk50)
begin
if (rst)
begin
pckt_data_in <= 0;
dm_done_prev <= 0;
dm_ack <= 0;
dm_arm <= 0;
end
else
begin
// retain states
dm_done_prev <= dm_done;
// measurement done
if (dm_done)
begin
pckt_data_in <= signed_delay;
dm_ack <= 1;
end
else
begin
dm_ack <= 0;
dm_arm <= 0;
end
// start button is pressed
if (dm_start)
begin
dm_arm <= 1;
end
// -----------------
// data is written to the memory
if (pckt_wrt)
begin
if (dm_enable)
begin
dm_arm <= 1;
end
end
end
end
assign ctrl_word[30:0] = 31'b0 | (FRAME_LENGTH << MEM_ADDR_WIDTH) | (0);
assign ctrl_word[31] = ~btn_prev && btn;
assign REF_CLK = clk50;
endmodule

109
src/packetizer.v Normal file
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@ -0,0 +1,109 @@
`timescale 1ns / 1ps
module packetizer #(
parameter MEM_WRITE_WIDTH = 16, // write size of the memory
//parameter MEM_READ_WIDTH = 8,
parameter MEM_DEPTH_BYTE = 1024, // depth of the memory in bytes
parameter MAX_PACKET_SIZE = 1500,
// AUTOCALCULATED
parameter MEM_WRITE_MSB = MEM_WRITE_WIDTH - 1,
//parameter MEM_READ_MSB = MEM_READ_WIDTH - 1,
parameter MEM_DEPTH_MSB = $clog2(MEM_DEPTH_BYTE) - 1
)(
input clk, rst, clear, // general signals
output [31:0] mac_ctrl_word, // MAC control word
input [MEM_WRITE_MSB:0] data_in, // data input
input wrt, // write signal
output mem_wea, // memory write enable signal
output [MEM_WRITE_MSB:0] mem_data, // data going into the memory
output [MEM_DEPTH_MSB:0] mem_addr, // write address
input immtx, // trigger an immediate transmission of memory contents
output empty, // memory is empty
output full // memory is fully occupied
);
wire rstclr = rst || clear; // combined reset and clear
reg [MEM_DEPTH_MSB:0] wr_ptr; // write pointer
reg [MEM_DEPTH_MSB:0] rd_ptr; // read pointer
reg [MEM_DEPTH_MSB+1:0] level; // fill level
always @(*)
begin
if (wr_ptr < rd_ptr)
level <= {1'b0, wr_ptr} + MEM_DEPTH_BYTE - {1'b0, rd_ptr}; // |===w-----r===|
else
level <= wr_ptr - rd_ptr; // |---r===w---|
end
// write operations
always @(posedge clk)
begin
if (rstclr)
begin
wr_ptr <= 0;
end
else
begin
if (wrt && !full) // increase write pointer if possible
begin
wr_ptr <= wr_ptr + 1'b1;
end
end
end
// read operations
wire level_triggers_transmit = (level > MAX_PACKET_SIZE - 1);
wire transmit = level_triggers_transmit || (immtx && !empty && !level_transmit); // level or demand-based transmission trigger
always @(posedge clk)
begin
if (rstclr)
begin
rd_ptr <= 0;
end
else
begin
if (transmit)
begin
rd_ptr <= wr_ptr;
end
end
end
reg level_transmit;
always @(posedge clk)
begin
if (rstclr)
begin
level_transmit <= 0;
end
else
begin
if (level_triggers_transmit)
begin
level_transmit <= 1;
end
else if (immtx)
begin
level_transmit <= 0;
end
end
end
// combinatorial outputs
assign empty = (rd_ptr == wr_ptr);
assign full = (wr_ptr == (rd_ptr - 1'b1));
assign mem_wea = wrt && !full;
assign mem_data = data_in;
assign mem_addr = wr_ptr;
assign mac_ctrl_word = 0 | (transmit << 31) | (level << (MEM_DEPTH_MSB + 1)) | rd_ptr;
endmodule

108
src/port/logsys_xc6_top.v
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@ -1,18 +1,29 @@
`timescale 1ns / 1ps
module logsys_xc6_top(
input wire clk50M, // 50MHz clock input
input wire rstbt,
input clk50M, // 50MHz clock input
input rstbt,
inout wire [16:4] aio,
input wire [0:0] bt
inout [16:4] aio,
input [2:0] bt,
output cpld_mosi,
input cpld_miso,
output cpld_load,
output cpld_clk,
output cpld_rstn,
output cpld_jtagen
);
assign cpld_jtagen = 1'b0;
wire rst = ~rstbt;
/* Main Clock Generation module */
wire clk50M90;
wire clk50M0;
wire clk200M;
MainPLL main_pll (
// Clock in ports
@ -21,15 +32,46 @@ MainPLL main_pll (
// Clock out ports
.Out_50MHz_0(clk50M0),
.Out_50MHz_90(clk50M90), // OUT
.Out_200MHz(clk200M),
// Status and control signals
.RESET(rst) // IN
// .LOCKED(/*main_pll_locked*/) // OUT
);
/* CPLD IO controller */
wire [7:0] sw;
wire [7:0] leds;
io_controller io_ctrl_inst (
.clk(clk50M90),
.rst(rst),
.clear(1'b0),
.leds(leds),
.sw(sw),
.mosi(cpld_mosi),
.miso(cpld_miso),
.load(cpld_load),
.sclk(cpld_clk),
.rstn(cpld_rstn)
);
ODDR2 ref_clk_oddr (
.D0(1'b1),
.D1(1'b0),
.R(1'b0),
.S(1'b0),
.CE(1'b1),
.C0(clk50M0),
.C1(~clk50M0),
.Q(aio[12])
);
/* signals */
wire [1:0] TXD;
wire TXEN, REF_CLK;
wire TXEN;
//wire [1:0] RXD;
//wire CRS_DV;
@ -37,21 +79,16 @@ wire TXEN, REF_CLK;
// Unused pins
assign aio[14] = 1'b0;
assign aio[12] = 1'b0;
assign aio[10] = 1'b0;
assign aio[8] = 1'b0;
//assign aio[10] = 1'b0;
//assign aio[8] = 1'b0;
assign aio[6] = 1'b0;
assign aio[5] = 1'b0;
assign aio[4] = 1'b0;
// Inputs
//assign RXD[0] = aio[11];
//assign RXD[1] = aio[9];
//assign CRS_DV = aio[7];
//
//assign aio[11] = 1'bZ;
//assign aio[9] = 1'bZ;
//assign aio[7] = 1'bZ;
assign aio[11] = 1'b0;
assign aio[9] = 1'b0;
assign aio[7] = 1'b0;
@ -60,18 +97,55 @@ assign aio[7] = 1'b0;
assign aio[16] = TXD[0];
assign aio[15] = TXD[1];
assign aio[13] = TXEN;
//assign aio[5] = REF_CLK;
assign aio[5] = clk50M0;
//assign aio[12] = REF_CLK;
//assign aio[12] = clk50M0;
/* input synchronization */
wire sig;
wire ref;
wire [2:0] bt_synced;
isync ref_isync (
.clk(clk200M),
.rst(rst),
.in(aio[8]),
.out(ref)
);
isync sig_isync (
.clk(clk200M),
.rst(rst),
.in(aio[10]),
.out(sig)
);
isync #(
.WIDTH(3)
) btn_isync (
.clk(clk50M90),
.rst(rst),
.in(bt),
.out(bt_synced)
);
/* JitMeas module */
jitmeas_top jitmeas_inst (
.clk50(clk50M90),
.clk200(clk200M),
.rst(rst),
.clear(1'b0),
.btn(bt[0]),
.btn(bt_synced),
.leds(leds),
.sw(sw),
.sig(sig),
.ref(ref),
.REF_CLK(REF_CLK),
//.RXD(RXD),
//.CRS_DV(CRS_DV),

2
src/rmii/rmii_transmit_controller.v
View File

@ -4,7 +4,7 @@
`include "src/rmii/rmii_serializer.v"
module rmii_transmit_controller #(
parameter FIFO_DEPTH = 16,
parameter FIFO_DEPTH = 4,
parameter STORAGE_WIDTH = 8,
// AUTOCALCULATED

48
src/sim/clk_div_test.v Normal file
View File

@ -0,0 +1,48 @@
`timescale 1ns / 1ps
`include "src/clkdiv.v"
module clk_div_test;
// Inputs
reg clk;
reg rst;
reg clear;
// Outputs
wire pos;
wire neg;
wire sclk;
// Instantiate the Unit Under Test (UUT)
clkdiv #(
.DIV(4)
) uut (
.clk(clk),
.rst(rst),
.clear(clear),
.pos(pos),
.neg(neg),
.sclk(sclk)
);
always #10 clk <= ~clk;
initial begin
// Initialize Inputs
clk <= 0;
rst <= 1;
clear <= 0;
// Wait 100 ns for global reset to finish
#20;
rst <= 0;
// Add stimulus here
#1000;
$finish;
end
endmodule

122
src/sim/del_meas_test.v Normal file
View File

@ -0,0 +1,122 @@
`timescale 1ns / 1ps
`include "src/del_meas/del_meas.v"
module del_meas_test;
// Inputs
reg clk;
reg rst;
reg clear;
reg ref;
reg sig;
reg arm;
reg ack;
// Outputs
wire listening;
wire done;
wire negative;
wire [9:0] delay;
// Instantiate the Unit Under Test (UUT)
del_meas uut (
.clk(clk),
.rst(rst),
.clear(clear),
.ref(ref),
.sig(sig),
.arm(arm),
.listening(listening),
.done(done),
.ack(ack),
.negative(negative),
.delay(delay)
);
localparam CLK_PERIOD = 5;
localparam CLK_HALFPERIOD = 5 / 2.0;
always #(CLK_HALFPERIOD) clk <= ~clk;
reg sclk;
always #10 sclk <= ~sclk;
reg start;
integer signed_delay;
always @(posedge sclk)
begin
if (done || start)
begin
if (done)
begin
signed_delay = delay;
if (negative) signed_delay = -signed_delay;
signed_delay = signed_delay * CLK_PERIOD;
$display("%d", signed_delay);
ack <= 1;
end
arm <= 1;
end
else
begin
ack <= 0;
arm <= 0;
end
end
initial begin
// Initialize Inputs
clk <= 0;
rst <= 1;
clear <= 0;
ref <= 0;
sig <= 0;
arm <= 0;
ack <= 0;
sclk <= 0;
signed_delay = 0;
start <= 0;
// Wait 20 ns for global reset to finish
#20;
rst <= 0;
#20;
start <= 1;
@(posedge sclk);
start <= 0;
#20;
ref <= 1;
#50;
sig <= 1;
#30;
ref <= 0;
#40;
sig <= 0;
#50;
sig <= 1;
#25;
ref <= 1;
#50;
sig <= 0;
ref <= 0;
#20;
// Add stimulus here
$finish;
end
endmodule

2
src/sim/eth_mac_test.v
View File

@ -38,7 +38,7 @@ module eth_mac_test;
// frame data
localparam FRAME_ADDR = 0;
localparam FRAME_LENGTH = 100;
localparam FRAME_LENGTH = 10;
localparam START = (1 << 31);
// RMII deserializer

1
src/sim/frame_recv.txt Normal file
View File

@ -0,0 +1 @@
LLorem ipsum olor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui officia deserunt mollit anim id est laborum.

93
src/sim/io_controller_test.v Normal file
View File

@ -0,0 +1,93 @@
`timescale 1ns / 1ps
module io_controller_test;
reg [7:0] SW;
reg [7:0] LEDS;
reg [3:0] IDX;
// Inputs
reg clk;
reg rst;
reg clear;
reg [7:0] leds;
// Outputs
wire [7:0] sw;
wire mosi;
wire miso;
wire load;
wire sclk;
wire rstn;
// Instantiate the Unit Under Test (UUT)
io_controller #(
.CLK_DIV(4)
) uut (
.clk(clk),
.rst(rst),
.clear(clear),
.leds(leds),
.sw(sw),
.mosi(mosi),
.miso(miso),
.load(load),
.sclk(sclk),
.rstn(rstn)
);
always #1 clk <= ~clk;
always @(posedge load)
begin
SW <= $random;
leds <= $random;
end
assign miso = work[0];
reg [15:0] work;
always @(posedge sclk)
begin
if (rst)
begin
work <= 16'h0000;
IDX <= 0;
end
else
begin
work <= {mosi, work[15:1]};
IDX <= IDX + 1;
if (load)
begin
LEDS <= work[8:1];
work <= {8'b0, SW};
IDX <= 0;
end
end
end
initial begin
// Initialize Inputs
clk <= 0;
rst <= 1;
clear <= 0;
leds <= $random | 1;
LEDS <= 0;
SW <= $random | 1;
IDX <= 0;
work <= 0;
// Wait 100 ns for global reset to finish
#2;
rst <= 0;
// Add stimulus here
#1000;
$finish;
end
endmodule

1
src/sim/rmii_transmit_controller_test.v
View File

@ -1,7 +1,6 @@
`timescale 1ns / 500ps
`include "src/rmii/rmii_transmit_controller.v"
`include "src/rmii/rmii_clock_generator.v"
module rmii_transmit_controller_test;

448
src/stream_mem_init.cgf
View File

@ -1,5 +1,5 @@
#version3.0
#memory_block_name=stream_init
#memory_block_name=lorem_ipsum_frame
#block_depth=4096
#data_width=8
#default_word=0
@ -10,4 +10,450 @@
#coe_radix=MEMORY_INITIALIZATION_RADIX
#coe_data=MEMORY_INITIALIZATION_VECTOR
#data=
@0
4C
6F
72
65
6D
20
69
70
73
75
6D
20
64
6F
6C
6F
72
20
73
69
74
20
61
6D
65
74
2C
20
63
6F
6E
73
65
63
74
65
74
75
72
20
61
64
69
70
69
73
63
69
6E
67
20
65
6C
69
74
2C
20
73
65
64
20
64
6F
20
65
69
75
73
6D
6F
64
20
74
65
6D
70
6F
72
20
69
6E
63
69
64
69
64
75
6E
74
20
75
74
20
6C
61
62
6F
72
65
20
65
74
20
64
6F
6C
6F
72
65
20
6D
61
67
6E
61
20
61
6C
69
71
75
61
2E
20
55
74
20
65
6E
69
6D
20
61
64
20
6D
69
6E
69
6D
20
76
65
6E
69
61
6D
2C
20
71
75
69
73
20
6E
6F
73
74
72
75
64
20
65
78
65
72
63
69
74
61
74
69
6F
6E
20
75
6C
6C
61
6D
63
6F
20
6C
61
62
6F
72
69
73
20
6E
69
73
69
20
75
74
20
61
6C
69
71
75
69
70
20
65
78
20
65
61
20
63
6F
6D
6D
6F
64
6F
20
63
6F
6E
73
65
71
75
61
74
2E
20
44
75
69
73
20
61
75
74
65
20
69
72
75
72
65
20
64
6F
6C
6F
72
20
69
6E
20
72
65
70
72
65
68
65
6E
64
65
72
69
74
20
69
6E
20
76
6F
6C
75
70
74
61
74
65
20
76
65
6C
69
74
20
65
73
73
65
20
63
69
6C
6C
75
6D
20
64
6F
6C
6F
72
65
20
65
75
20
66
75
67
69
61
74
20
6E
75
6C
6C
61
20
70
61
72
69
61
74
75
72
2E
20
45
78
63
65
70
74
65
75
72
20
73
69
6E
74
20
6F
63
63
61
65
63
61
74
20
63
75
70
69
64
61
74
61
74
20
6E
6F
6E
20
70
72
6F
69
64
65
6E
74
2C
20
73
75
6E
74
20
69
6E
20
63
75
6C
70
61
20
71
75
69
20
6F
66
66
69
63
69
61
20
64
65
73
65
72
75
6E
74
20
6D
6F
6C
6C
69
74
20
61
6E
69
6D
20
69
64
20
65
73
74
20
6C
61
62
6F
72
75
6D
2E
#end

0
src/lorem_ipsum_frame.coe → src/stream_mem_init_lorem_ipsum_frame.coe
View File

46
wcfg/crc32.wcfg Normal file
View File

@ -0,0 +1,46 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/DEV/S6_RMII/crc32_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="crc32_test" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="7" />
<wvobject fp_name="/crc32_test/crc_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">crc_out[31:0]</obj_property>
<obj_property name="ObjectShortName">crc_out[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="Reversed">false</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/clear" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clear</obj_property>
<obj_property name="ObjectShortName">clear</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[7:0]</obj_property>
<obj_property name="ObjectShortName">data_in[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/crc_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">crc_en</obj_property>
<obj_property name="ObjectShortName">crc_en</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/ifile" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ifile[31:0]</obj_property>
<obj_property name="ObjectShortName">ifile[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wave_config>

144
wcfg/del_meas.wcfg Normal file
View File

@ -0,0 +1,144 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/DEV/S6_RMII/del_meas_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="del_meas_test" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="30" />
<wvobject fp_name="/del_meas_test/listening" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">listening</obj_property>
<obj_property name="ObjectShortName">listening</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">done</obj_property>
<obj_property name="ObjectShortName">done</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/negative" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">negative</obj_property>
<obj_property name="ObjectShortName">negative</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/delay" type="array" db_ref_id="1">
<obj_property name="ElementShortName">delay[9:0]</obj_property>
<obj_property name="ObjectShortName">delay[9:0]</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/clear" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clear</obj_property>
<obj_property name="ObjectShortName">clear</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/ref" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ref</obj_property>
<obj_property name="ObjectShortName">ref</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/sig" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sig</obj_property>
<obj_property name="ObjectShortName">sig</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/arm" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">arm</obj_property>
<obj_property name="ObjectShortName">arm</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack</obj_property>
<obj_property name="ObjectShortName">ack</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/sclk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sclk</obj_property>
<obj_property name="ObjectShortName">sclk</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/start" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">start</obj_property>
<obj_property name="ObjectShortName">start</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/signed_delay" type="array" db_ref_id="1">
<obj_property name="ElementShortName">signed_delay[31:0]</obj_property>
<obj_property name="ObjectShortName">signed_delay[31:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/CLK_PERIOD" type="array" db_ref_id="1">
<obj_property name="ElementShortName">CLK_PERIOD[31:0]</obj_property>
<obj_property name="ObjectShortName">CLK_PERIOD[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/CLK_HALFPERIOD" type="other" db_ref_id="1">
<obj_property name="ElementShortName">CLK_HALFPERIOD</obj_property>
<obj_property name="ObjectShortName">CLK_HALFPERIOD</obj_property>
</wvobject>
<wvobject fp_name="divider19" type="divider">
<obj_property name="label">DELMEAS</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/ref" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ref</obj_property>
<obj_property name="ObjectShortName">ref</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/ref_edge" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ref_edge</obj_property>
<obj_property name="ObjectShortName">ref_edge</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/sig" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sig</obj_property>
<obj_property name="ObjectShortName">sig</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/sig_edge" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sig_edge</obj_property>
<obj_property name="ObjectShortName">sig_edge</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/arm" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">arm</obj_property>
<obj_property name="ObjectShortName">arm</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/arm_edge" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">arm_edge</obj_property>
<obj_property name="ObjectShortName">arm_edge</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack</obj_property>
<obj_property name="ObjectShortName">ack</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/ack_pulse" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_pulse</obj_property>
<obj_property name="ObjectShortName">ack_pulse</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/negative" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">negative</obj_property>
<obj_property name="ObjectShortName">negative</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/delay" type="array" db_ref_id="1">
<obj_property name="ElementShortName">delay[9:0]</obj_property>
<obj_property name="ObjectShortName">delay[9:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/listening" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">listening</obj_property>
<obj_property name="ObjectShortName">listening</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">done</obj_property>
<obj_property name="ObjectShortName">done</obj_property>
</wvobject>
<wvobject fp_name="/del_meas_test/uut/state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">state[3:0]</obj_property>
<obj_property name="ObjectShortName">state[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>

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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/DEV/S6_RMII/eth_mac_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="eth_mac_test" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="26" />
<wvobject fp_name="/eth_mac_test/mem_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_data[7:0]</obj_property>
<obj_property name="ObjectShortName">mem_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/mem_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_data[7:0]</obj_property>
<obj_property name="ObjectShortName">mem_data[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/mem_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_addr[11:0]</obj_property>
<obj_property name="ObjectShortName">mem_addr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/TXEN" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">TXEN</obj_property>
<obj_property name="ObjectShortName">TXEN</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/TXD" type="array" db_ref_id="1">
<obj_property name="ElementShortName">TXD[1:0]</obj_property>
<obj_property name="ObjectShortName">TXD[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/deser" type="array" db_ref_id="1">
<obj_property name="ElementShortName">deser[7:0]</obj_property>
<obj_property name="ObjectShortName">deser[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/deser" type="array" db_ref_id="1">
<obj_property name="ElementShortName">deser[7:0]</obj_property>
<obj_property name="ObjectShortName">deser[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/ctrl_word" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_word[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_word[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/mem" type="array" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">mem[0:444,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[0:444,7:0]</obj_property>
<obj_property name="label">mem[25:0,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider2094" type="divider">
<obj_property name="label">MEM ACC CTRL</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/transmitter_busy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">transmitter_busy</obj_property>
<obj_property name="ObjectShortName">transmitter_busy</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/start" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">start</obj_property>
<obj_property name="ObjectShortName">start</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/frame_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">frame_addr[11:0]</obj_property>
<obj_property name="ObjectShortName">frame_addr[11:0]</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/frame_len" type="array" db_ref_id="1">
<obj_property name="ElementShortName">frame_len[10:0]</obj_property>
<obj_property name="ObjectShortName">frame_len[10:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/busy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">busy</obj_property>
<obj_property name="ObjectShortName">busy</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/tx_data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">tx_data_in[7:0]</obj_property>
<obj_property name="ObjectShortName">tx_data_in[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/tx_data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">tx_data_in[7:0]</obj_property>
<obj_property name="ObjectShortName">tx_data_in[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/tx_not_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">tx_not_full</obj_property>
<obj_property name="ObjectShortName">tx_not_full</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/tx_wrt" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">tx_wrt</obj_property>
<obj_property name="ObjectShortName">tx_wrt</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">state[2:0]</obj_property>
<obj_property name="ObjectShortName">state[2:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/len_left" type="array" db_ref_id="1">
<obj_property name="ElementShortName">len_left[10:0]</obj_property>
<obj_property name="ObjectShortName">len_left[10:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/mem_acc_ctrl/crc_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">crc_out[31:0]</obj_property>
<obj_property name="ObjectShortName">crc_out[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider125" type="divider">
<obj_property name="label">SERIALIZER</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/tx_ctrl/tx_fifo/mem" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem[3:0,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[3:0,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
<wvobject fp_name="/eth_mac_test/uut/tx_ctrl/tx_fifo/mem[3]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[3,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[3,7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/tx_ctrl/tx_fifo/mem[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[2,7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/tx_ctrl/tx_fifo/mem[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[1,7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/eth_mac_test/uut/tx_ctrl/tx_fifo/mem[0]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[0,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[0,7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wvobject>
</wave_config>

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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/DEV/S6_RMII/fifo_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="fifo_test" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="20" />
<wvobject fp_name="/fifo_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out[7:0]</obj_property>
<obj_property name="ObjectShortName">out[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">empty</obj_property>
<obj_property name="ObjectShortName">empty</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/out_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_valid</obj_property>
<obj_property name="ObjectShortName">out_valid</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">full</obj_property>
<obj_property name="ObjectShortName">full</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff0000</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/clear" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clear</obj_property>
<obj_property name="ObjectShortName">clear</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in[7:0]</obj_property>
<obj_property name="ObjectShortName">in[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffa500</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/push" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">push</obj_property>
<obj_property name="ObjectShortName">push</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/pop" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">pop</obj_property>
<obj_property name="ObjectShortName">pop</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/ifile" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ifile[31:0]</obj_property>
<obj_property name="ObjectShortName">ifile[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/c" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c[31:0]</obj_property>
<obj_property name="ObjectShortName">c[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider28" type="divider">
<obj_property name="label">FIFO</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/mem" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem[7:0,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[7:0,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
<wvobject fp_name="/fifo_test/uut/mem[7]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[7,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[7,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/mem[6]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[6,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[6,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/mem[5]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[5,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[5,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/mem[4]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[4,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[4,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/mem[3]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[3,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[3,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/mem[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[2,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/mem[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[1,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/mem[0]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[0,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[0,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/fifo_test/uut/push_idx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">push_idx[2:0]</obj_property>
<obj_property name="ObjectShortName">push_idx[2:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/pop_idx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pop_idx[2:0]</obj_property>
<obj_property name="ObjectShortName">pop_idx[2:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/level" type="array" db_ref_id="1">
<obj_property name="ElementShortName">level[3:0]</obj_property>
<obj_property name="ObjectShortName">level[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#00ffff</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/out_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_valid</obj_property>
<obj_property name="ObjectShortName">out_valid</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/will_pop" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">will_pop</obj_property>
<obj_property name="ObjectShortName">will_pop</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/fifo_test/uut/will_push" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">will_push</obj_property>
<obj_property name="ObjectShortName">will_push</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
</wave_config>

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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/DEV/S6_RMII/io_controller_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="io_controller_test" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="21" />
<wvobject fp_name="/io_controller_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/sclk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sclk</obj_property>
<obj_property name="ObjectShortName">sclk</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/mosi" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mosi</obj_property>
<obj_property name="ObjectShortName">mosi</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/miso" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">miso</obj_property>
<obj_property name="ObjectShortName">miso</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffa500</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/load" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">load</obj_property>
<obj_property name="ObjectShortName">load</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/SW" type="array" db_ref_id="1">
<obj_property name="ElementShortName">SW[7:0]</obj_property>
<obj_property name="ObjectShortName">SW[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#00ffff</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/SW" type="array" db_ref_id="1">
<obj_property name="ElementShortName">SW[7:0]</obj_property>
<obj_property name="ObjectShortName">SW[7:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#00ffff</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/LEDS" type="array" db_ref_id="1">
<obj_property name="ElementShortName">LEDS[7:0]</obj_property>
<obj_property name="ObjectShortName">LEDS[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/LEDS" type="array" db_ref_id="1">
<obj_property name="ElementShortName">LEDS[7:0]</obj_property>
<obj_property name="ObjectShortName">LEDS[7:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/IDX" type="array" db_ref_id="1">
<obj_property name="ElementShortName">IDX[3:0]</obj_property>
<obj_property name="ObjectShortName">IDX[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/clear" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clear</obj_property>
<obj_property name="ObjectShortName">clear</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/sw" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sw[7:0]</obj_property>
<obj_property name="ObjectShortName">sw[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/work" type="array" db_ref_id="1">
<obj_property name="ElementShortName">work[15:0]</obj_property>
<obj_property name="ObjectShortName">work[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider49" type="divider">
<obj_property name="label">IO CONTROLLER</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/uut/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[15:0]</obj_property>
<obj_property name="ObjectShortName">data[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/uut/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[15:0]</obj_property>
<obj_property name="ObjectShortName">data[15:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/uut/sw" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sw[7:0]</obj_property>
<obj_property name="ObjectShortName">sw[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/uut/leds" type="array" db_ref_id="1">
<obj_property name="ElementShortName">leds[7:0]</obj_property>
<obj_property name="ObjectShortName">leds[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/uut/leds" type="array" db_ref_id="1">
<obj_property name="ElementShortName">leds[7:0]</obj_property>
<obj_property name="ObjectShortName">leds[7:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/io_controller_test/uut/idx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">idx[3:0]</obj_property>
<obj_property name="ObjectShortName">idx[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>

79
wcfg/rmii_ctrl.wcfg Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/DEV/S6_RMII/rmii_ctrl_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="rmii_ctrl_test" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="15" />
<wvobject fp_name="/rmii_ctrl_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/REF_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">REF_CLK</obj_property>
<obj_property name="ObjectShortName">REF_CLK</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/TXD" type="array" db_ref_id="1">
<obj_property name="ElementShortName">TXD[1:0]</obj_property>
<obj_property name="ObjectShortName">TXD[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/TXEN" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">TXEN</obj_property>
<obj_property name="ObjectShortName">TXEN</obj_property>
</wvobject>
<wvobject fp_name="divider15" type="divider">
<obj_property name="label">RMII_CLOCK_GENERATOR</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/REF_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">REF_CLK</obj_property>
<obj_property name="ObjectShortName">REF_CLK</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/rising" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rising</obj_property>
<obj_property name="ObjectShortName">rising</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/falling" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">falling</obj_property>
<obj_property name="ObjectShortName">falling</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/ref_clk_cntr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ref_clk_cntr[1:0]</obj_property>
<obj_property name="ObjectShortName">ref_clk_cntr[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/MAIN_CLK_FREQ" type="array" db_ref_id="1">
<obj_property name="ElementShortName">MAIN_CLK_FREQ[31:0]</obj_property>
<obj_property name="ObjectShortName">MAIN_CLK_FREQ[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/CNTR_WIDTH" type="array" db_ref_id="1">
<obj_property name="ElementShortName">CNTR_WIDTH[31:0]</obj_property>
<obj_property name="ObjectShortName">CNTR_WIDTH[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/CNTR_MSB" type="array" db_ref_id="1">
<obj_property name="ElementShortName">CNTR_MSB[31:0]</obj_property>
<obj_property name="ObjectShortName">CNTR_MSB[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>

245
wcfg/rmii_tx_ctrl.wcfg Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/DEV/S6_RMII/rmii_transmit_controller_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="rmii_transmit_controller_test" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="33" />
<wvobject fp_name="/rmii_transmit_controller_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/clear" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clear</obj_property>
<obj_property name="ObjectShortName">clear</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/not_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">not_full</obj_property>
<obj_property name="ObjectShortName">not_full</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/busy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">busy</obj_property>
<obj_property name="ObjectShortName">busy</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/TXEN" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">TXEN</obj_property>
<obj_property name="ObjectShortName">TXEN</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/TXD" type="array" db_ref_id="1">
<obj_property name="ElementShortName">TXD[1:0]</obj_property>
<obj_property name="ObjectShortName">TXD[1:0]</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffff00</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[7:0]</obj_property>
<obj_property name="ObjectShortName">data_in[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/wrt" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wrt</obj_property>
<obj_property name="ObjectShortName">wrt</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/run" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">run</obj_property>
<obj_property name="ObjectShortName">run</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/start" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">start</obj_property>
<obj_property name="ObjectShortName">start</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/c" type="array" db_ref_id="1">
<obj_property name="ElementShortName">c[31:0]</obj_property>
<obj_property name="ObjectShortName">c[31:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/wrt_cntr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wrt_cntr[31:0]</obj_property>
<obj_property name="ObjectShortName">wrt_cntr[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/deser" type="array" db_ref_id="1">
<obj_property name="ElementShortName">deser[7:0]</obj_property>
<obj_property name="ObjectShortName">deser[7:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/deser" type="array" db_ref_id="1">
<obj_property name="ElementShortName">deser[7:0]</obj_property>
<obj_property name="ObjectShortName">deser[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider19" type="divider">
<obj_property name="label">SERIALIZER</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/out_serializer/par_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">par_in[7:0]</obj_property>
<obj_property name="ObjectShortName">par_in[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/out_serializer/load" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">load</obj_property>
<obj_property name="ObjectShortName">load</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/out_serializer/shift" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">shift</obj_property>
<obj_property name="ObjectShortName">shift</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/out_serializer/empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">empty</obj_property>
<obj_property name="ObjectShortName">empty</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/out_serializer/exhausted" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">exhausted</obj_property>
<obj_property name="ObjectShortName">exhausted</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/out_serializer/single" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">single</obj_property>
<obj_property name="ObjectShortName">single</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/out_serializer/shift_work" type="array" db_ref_id="1">
<obj_property name="ElementShortName">shift_work[7:0]</obj_property>
<obj_property name="ObjectShortName">shift_work[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/out_serializer/shift_work" type="array" db_ref_id="1">
<obj_property name="ElementShortName">shift_work[7:0]</obj_property>
<obj_property name="ObjectShortName">shift_work[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/out_serializer/shift_count" type="array" db_ref_id="1">
<obj_property name="ElementShortName">shift_count[1:0]</obj_property>
<obj_property name="ObjectShortName">shift_count[1:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider26" type="divider">
<obj_property name="label">FIFO</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in[7:0]</obj_property>
<obj_property name="ObjectShortName">in[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/push" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">push</obj_property>
<obj_property name="ObjectShortName">push</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/pop" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">pop</obj_property>
<obj_property name="ObjectShortName">pop</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">empty</obj_property>
<obj_property name="ObjectShortName">empty</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">full</obj_property>
<obj_property name="ObjectShortName">full</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/level" type="array" db_ref_id="1">
<obj_property name="ElementShortName">level[4:0]</obj_property>
<obj_property name="ObjectShortName">level[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem[15:0,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[15:0,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[15]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[15,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[15,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[14]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[14,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[14,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[13]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[13,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[13,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[12]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[12,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[12,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[11]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[11,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[11,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[10]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[10,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[10,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[9]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[9,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[9,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[8]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[8,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[8,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[7]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[7,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[7,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[6]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[6,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[6,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[5]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[5,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[5,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[4]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[4,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[4,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[3]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[3,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[3,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[2,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[1,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_transmit_controller_test/uut/tx_fifo/mem[0]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[0,7:0]</obj_property>
<obj_property name="ObjectShortName">mem[0,7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
</wvobject>
</wave_config>