JitMeas-verilog/wcfg/rmii_ctrl.wcfg
2024-12-05 09:57:10 +01:00

80 lines
4.1 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/DEV/S6_RMII/rmii_ctrl_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="rmii_ctrl_test" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="15" />
<wvobject fp_name="/rmii_ctrl_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/REF_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">REF_CLK</obj_property>
<obj_property name="ObjectShortName">REF_CLK</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/TXD" type="array" db_ref_id="1">
<obj_property name="ElementShortName">TXD[1:0]</obj_property>
<obj_property name="ObjectShortName">TXD[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/TXEN" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">TXEN</obj_property>
<obj_property name="ObjectShortName">TXEN</obj_property>
</wvobject>
<wvobject fp_name="divider15" type="divider">
<obj_property name="label">RMII_CLOCK_GENERATOR</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/REF_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">REF_CLK</obj_property>
<obj_property name="ObjectShortName">REF_CLK</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/rising" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rising</obj_property>
<obj_property name="ObjectShortName">rising</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/falling" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">falling</obj_property>
<obj_property name="ObjectShortName">falling</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/ref_clk_cntr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ref_clk_cntr[1:0]</obj_property>
<obj_property name="ObjectShortName">ref_clk_cntr[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/MAIN_CLK_FREQ" type="array" db_ref_id="1">
<obj_property name="ElementShortName">MAIN_CLK_FREQ[31:0]</obj_property>
<obj_property name="ObjectShortName">MAIN_CLK_FREQ[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/CNTR_WIDTH" type="array" db_ref_id="1">
<obj_property name="ElementShortName">CNTR_WIDTH[31:0]</obj_property>
<obj_property name="ObjectShortName">CNTR_WIDTH[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/rmii_ctrl_test/uut/clk_gen/CNTR_MSB" type="array" db_ref_id="1">
<obj_property name="ElementShortName">CNTR_MSB[31:0]</obj_property>
<obj_property name="ObjectShortName">CNTR_MSB[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>