epagris/JitMeas-verilog
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Wiesner András 038be21f4f initial
2024-11-28 17:12:50 +01:00
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initial
2024-11-28 17:12:50 +01:00
sims
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2024-11-28 17:12:50 +01:00
Description
High-resolution jitter measurement system for the Xilinx Spartan-6 FPGA.
5.7 MiB
Languages
Verilog 95.8%
Shell 4.2%