94 lines
1.2 KiB
Verilog
94 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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`include "src/clkdiv.v"
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module io_controller #(
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parameter CLK_DIV = 100,
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parameter FRAME_SIZE = 16,
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// AUTOCALCULATED
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parameter FRAME_IDX_MSB = $clog2(FRAME_SIZE - 1) - 1
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)(
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input clk, rst, clear,
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input [7:0] leds,
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output reg [7:0] sw,
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output mosi,
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input miso,
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output load,
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output sclk,
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output rstn
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);
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wire rstclr = rst || clear;
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wire strobe;
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clkdiv #(
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.DIV(CLK_DIV)
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) sclk_div (
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.clk(clk),
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.rst(rst),
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.clear(clear),
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.sclk(sclk),
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.pos(),
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.neg(strobe)
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);
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reg [FRAME_SIZE-1:0] data;
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reg [FRAME_IDX_MSB:0] idx;
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always @(posedge clk)
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begin
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if (rstclr)
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begin
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data <= 0;
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sw <= 0;
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end
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else
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begin
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if (strobe)
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begin
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if (idx == (FRAME_SIZE - 1'b1))
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begin
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sw <= data[7:0];
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data <= {miso, 7'b0, leds};
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end
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else
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begin
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data <= {miso, data[15:1]};
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end
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end
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end
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end
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always @(posedge clk)
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begin
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if (rstclr)
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begin
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idx <= (FRAME_SIZE - 1'b1);
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end
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else
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begin
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if (strobe)
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begin
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if (idx == (FRAME_SIZE - 1'b1))
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begin
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idx <= 0;
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end
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else
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begin
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idx <= idx + 1'b1;
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end
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end
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end
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end
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assign rstn = !rstclr;
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assign load = idx == (FRAME_SIZE - 1'b1);
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assign mosi = data[0];
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endmodule
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