JitMeas-verilog/wcfg/crc32.wcfg
2024-12-05 09:57:10 +01:00

47 lines
2.1 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/DEV/S6_RMII/crc32_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="crc32_test" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="7" />
<wvobject fp_name="/crc32_test/crc_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">crc_out[31:0]</obj_property>
<obj_property name="ObjectShortName">crc_out[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="Reversed">false</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/clear" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clear</obj_property>
<obj_property name="ObjectShortName">clear</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[7:0]</obj_property>
<obj_property name="ObjectShortName">data_in[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/crc_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">crc_en</obj_property>
<obj_property name="ObjectShortName">crc_en</obj_property>
</wvobject>
<wvobject fp_name="/crc32_test/ifile" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ifile[31:0]</obj_property>
<obj_property name="ObjectShortName">ifile[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wave_config>